The invention relates to an FET forming a non-volatile memory cell and having a source and a drain zone and a floating-gate electrode as the memory electrode between which and the semiconductor element is arranged to a tunnel-through dielectric layer, and to the use of such a memory cell. The invention further relates to a method for manufacture of such a memory cell.
A non-volatile memory cell of this type is known from "Nichtfluchtige Speicher: EEPROM's und KNRAM's", electronic FIG. 1, where a FLOTOX (Floating-Gate-Tunnel-Oxide) memory transistor developed by Intel for EEPROMs eelectrically erasable programmable read only memory is illustrated and described.
A FLOTOX cell of this type is electrically erasable and represents a further development of the UV-erasable cells. Whereas in the latter avalanche injection dominates during programming and erasing, i.e. discharging of the gate is achieved by exciting the electrons with UV radiation, in EEPROM cells the tunnel mechanism of the electrons according to Fowler-Nordheim is exploited in the vertical direction for programming and erasing.
With the FLOTOX memory transistor from Intel in accordance with the above reference, the tunnel oxide is above the drain zone. Depending on the potentials applied to the electrodes, an electrical field is generated in the tunnel oxide that either triggers the passage of electrons from the drain zone onto the floating gate--representing the "logic 1"state--or discharges the floating gate as the electrons tunnel back to the drain zone, thereby programming "logic 0". Each memory cell has for selectrion of the memory cells an NMOS transistor connected in series to the FLOTOX transistor.
In the following, the manufacture of a known FLOTOX memory cell of this type is described with the aid of FIGS. 1 to 3.
In accordance with FIG. 1, a gate oxide 3 and a first photoresist coating is deposited on an n-doped semiconductor substrate 1 after production of the active areas and of a P-through 4. An n.sup.+ -doped area 6 is created in the semiconductor substrate 1 through an opening in the photoresist in order to produce the drain zone by means of ion implantation.
A second photoresist step with subsequent etching of the gate oxide 3 defines the tunnel window above the n.sup.+ -doped area 6 in accordance with FIG. 2. This is followed by the production of tunnel oxide layer 11 with a thickness of approximately 100 .ANG.and the deposition of the first polysilicon level, which is treated in a further photolithography and etching step to make the floating-gate electrode 12. The further process sequence starts as shown in FIG. 3 with the production of the Interpoly insulation layer 13 and is continued with the provision of the n.sup.+ -doped source zone 15 by means of ion implantation.
A second polysilicon level is then applied to produce gate electrode 14, and the surface is then covered completely with an insulation layer 16. Finally, the contact-hole areas 12, are generated in a final photolithography and etching step and the aluminum conductive paths 18 are vapour-deposited. Finally, the entire surface is covered with a passivation layer 19.
Drawbacks of this conventional technology are in the definition of the tunnel window by photolithography steps. The design of the memory cells must be such that the tunnel window is above the n.sup.30 area 6 and its edge do not reach the edges of the active area. This puts heavy demands on the adjustment accuracy and restricts at the same time the minimization of the design by masking. In addition, the size of the tunnel window can be reduced at acceptable expense only to 2 .mu.m .times.2.mu.m.